1. Field of the Invention
This invention relates generally to a hardware arrangement for detecting error and storing information thereof in a pipelined data processing system and a method therefor, and more specifically to such an arrangement and method which enable a simplification in the hardware configuration.
2. Description of the Prior Art
Pipelining is a hardware technique for achieving higher performance by breaking a complex, time-consuming function into a series of simpler, shorter operations, each of which can then be executed in assembly-line fashion with simultaneous computation on different sets of data.
It is a common practice in a pipelined data processing system to check for a malfunction in each of the processing sub-stages of a pipeline. However, a conventional hardware arrangement for detecting error and storing information thereof in a pipelined data processing system, has encountered the problem that it is rather complex and hence not suitable for large scale circuit integration by way of example.
Before describing in detail the present invention an arrangement known to the present applicant will be described with reference to FIG. 1. It should be noted that a control network for the FIG. 1 arrangement is not shown for simplifying the description of the drawing and facilitating the description of the arrangement.
As shown in FIG. 1, a pipeline 10 includes four serially coupled stages 12, 14, 16 and 18, which perform, merely by way of example, instruction fetch, instruction decode, address generation, and operand fetch, respectively. Each of the stages 12, 14, 16 and 18 includes a local storage sub-stage (12a, 14a, 16a or 18a) followed by a data or instruction processing substage (12b, 14b, 16b or 18b). Each of the data processing sub-stages 12b through 18b manipulates data which is derived from the preceding local storage substage (12a, 14a, 16a or 18a).
The data processing sub-stages 12b, 14b, 16b and 18b are respectively coupled to error detectors 30, 32, 34 and 36, each of which is provided for detecting malfunction in the associated data processing sub-stage (12b, 14b, 16b or 18b).
It is assumed that the error detector 32 detects a malfunction in the associated data processing sub-stage 14b. Upon detection of the malfunction in the sub-stage 14b, the detector 32 applies a first error signal through an OR gate 38 to an error information storage means 40 which comprises memory sections 40a, 40b, 40c and 40d. The first error signal merely represents an error occurrence. Within the same operation cycle as the error detector 32 detects the malfunction in the substage 14b, a second error signal, containing error information for analyzing the detected error, is derived from the local storage sub-stage 14a and is stored in the memory section 40b of the error signal storage means 40.
Since the information storage means 40 stores both of the first and second error signals, it is necessary to save the error information within the same cycle as the error occurs to prevent it being erased at the next clock interval. Therefore, the error information storage means 40 is provided with the four memory sections 40a, 40b, 40c and 40d in this particular instance. Inasmuch as each of the memory sections 40a, 40b, 40c and 40d requires a large amount of memory (for example 32 or 64 bits) for storing the error information, it is highly desirable to limit the number of the memory sections.